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MPC755CE/D Rev. 2, 6/2002 MPC755 RISC Microprocessor Chip Errata
This document details all known silicon errata for the MPC755 and MPC745. Table 1 provides a revision history for this chip errata document.
Table 1. Document Revision History
Document Revision Revs. 0-1 Rev. 2 Significant Changes Earlier releases of document Added Errors 6 and 7
Table 2 describes the devices to which the errata in this document apply and provides a cross-reference to match the revision code in the processor version register to the revision level marked on the part.
Table 2. Revision Level to Part Marking Cross-Reference
MPC755 Revision 1.0 1.1 2.0 2.7 2.8 D E Part Marking Processor Version Register 0008 3100 0008 3101 0008 3200 0008 3202 0008 3203
Table 3 summarizes all known errata and lists the corresponding silicon revision level to which it applies. A `Y' entry indicates the erratum applies to a particular revision level, while a `--' entry means it does not apply.
2 Table 3. Summary of Silicon Errata and Applicable Revision
Present in Version: 1.0 The VOLTDET is connected to VDD Cannot use this signal to set Use alternative reference. rather than L2OVDD in the 360 BGA voltage reference for SRAM package. I/O (if required). Y 1.1 Y 2.x N Description Impact Work Around Y N N Y Y N Hits in the added BAT registers may New feature. not disable TLB interactions. The L2ZZ pin was tied low as a workaround for errata 2. Use the standard 4 IBAT and 4 DBAT registers only. Y N Y Y N N PB2: Cannot use this feature PB2: Use L2CR clock stop bit to put the SRAMs into a ZZ for same low power. power mode during sleep. PB3: None exists. PB3: Cannot use as ADS pin for this type of SRAM. L2 address parity cannot be None used. Y Y Y Systems requiring the ability to perform single-beat cache-inhibited stores while in L2 test mode may experience memory corruption or system hangs. 1. Use Private Memory mode to test L2 cache. OR 2. Configure cache-inhibited space as write-through (WIMG=11xx) if transactions must propagate to system bus Y Y Y
No.
Problem
1
VOLTDET in 360 BGA connected to VDD
2
L2ZZ pin incorrectly active The L2ZZ pin in PB2 mode is Cannot use this feature to put Do not connect the L2ZZ pin to low incorrectly made an active low signal. the SRAMs into a ZZ power the SRAM. saving mode.
3
System bus inoperable in In PLL bypass mode, incorrect data Cannot run the processor at None exists. PLL bypass mode. may be sampled from the system bus system bus speeds. interface.
4
Additional BAT registers non-functional
5
L2ZZ pin always low
MPC755 RISC Microprocessor Chip Errata
6
L2 address parity does not Incorrect parity may be generated work. when writing a cache line to the L2, causing a subsequent parity error when the cache line is read.
7
Single-beat, Single-beat, cache-inhibited stores cache-inhibited stores are discarded and do not propagate discarded in L2 test mode. to the system bus when L2 test support mode is enabled.
MOTOROLA
Error No. 1: VOLTDET in 360 BGA package connected to VDD
Overview:
The VOLTDET signal is connected to VDD rather than L2OVDD in the 360 BGA package.
Detailed Description:
The VOLTDET signal of the MPC755 (360 BGA) is intended to indicate the voltage level present at the L2 cache interface as a reference for SRAM I/O. In affected devices, however, this signal is internally connected to VDD rather than L2OVDD.
Projected Impact:
This signal cannot be used to set the voltage reference for SRAM I/O (if required).
Work Arounds:
An alternative reference may be used.
Projected Solution:
Fixed in MPC755 Rev. 2.0
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
3
Error No. 2: L2ZZ pin incorrectly active low
Overview:
The L2ZZ pin in PB2 mode is incorrectly made an active low signal.
Detailed Description:
The L2ZZ pin should be an active high output used to enable low-power mode for L2 memory devices supporting this feature. In affected devices, however, this signal is erroneously an active low output.
Projected Impact:
Cannot use this feature to put the SRAMs into a power-saving mode.
Work Around:
Do not use low-power mode feature of SRAM.
Projected Solution:
Fixed in MPC755 Rev. 1.1
4
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 3: System bus inoperable in PLL bypass mode.
Overview:
In PLL bypass mode, the system bus may be inoperable.
Detailed Description: In PLL-bypass mode, incorrect data may be captured from 60x bus interface, causing processor hangs and data corruption. Projected Impact:
Cannot operate in PLL bypass mode.
Work Arounds:
None
Projected Solution:
Fixed in MPC755 Rev. 2.0
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
5
Error No. 4: Additional BAT registers non-functional
Overview:
Hits in the added BAT registers may not disable TLB interactions.
Detailed Description:
During address translation, BAT registers are checked first. If an effective address hits in a BAT, the TLB should be ignored. In affected devices, however, an effective address that hits in one of the additional BAT registers will still propagate to the TLB, causing incorrect device behavior.
Projected Impact:
Additional BAT registers cannot be used.
Work Arounds:
Use the standard 4 IBAT and 4 DBAT registers only.
Projected Solution:
Fixed in MPC755 Rev. 2.0
6
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 5: L2ZZ pin always low
Overview:
The L2ZZ pin is internally tied low.
Detailed Description:
The L2ZZ pin should be an active high output used to enable low-power mode for L2 memory devices supporting this feature. In affected devices, however, this signal is erroneously tied low.
Projected Impact:
PB2: Cannot use this feature to put the SRAMs into a low-power mode during sleep. PB3: Cannot use as ADS pin for this type of SRAM.
Work Arounds:
None
Projected Solution:
Fixed in MPC755 Rev. 2.0
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
7
Error No. 6: L2 address parity does not work
Overview:
L2 address parity generation does not work correctly.
Detailed Description:
Incorrect parity may be generated when writing a cache line to the L2 cache. Because the correct algorithm is used when checking parity for a read, a parity error occurs when the cache line is subsequently read.
Projected Impact:
L2 address parity cannot be used.
Work Arounds:
None
Projected Solution:
Under review
8
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
Error No. 7: Single-beat, cache-inhibited stores discarded in L2 test mode.
Overview:
Single-beat, cache-inhibited stores are discarded when L2CR[L2TS] is set.
Detailed Description:
Single-beat, cache-inhibited stores are discarded and do not propagate to the system bus when L2 test support mode is enabled.
Projected Impact:
Systems requiring the ability to perform single-beat cache-inhibited stores while in L2 test mode may experience memory corruption or system hangs.
Work Around:
1. Use Private Memory mode to test the L2 cache. OR 2. Configure cache-inhibited space as write-through (WIMG=11xx) if transactions must propagate to system bus while in L2 test support mode. These settings are not defined in the architecture but are useful to overcome this erratum.
Projected Solution:
Under review
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
9
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10
MPC755 RISC Microprocessor Chip Errata
MOTOROLA
MOTOROLA
MPC755 RISC Microprocessor Chip Errata
11
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